1. Field of Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to structures of a split-gate non-volatile memory cell and a split-gate non-volatile memory array, and the methods for operating the same.
2. Description of Related Art
In the family of non-volatile memory devices, various electrically erasable programmable memory (E2PROM/Flash EPROM) devices have been widely used in personal computers and electronic apparatuses since they can be programmed and erased repeatedly, and can retain data even if disconnected from electrical power. A conventional E2PROM/Flash EPROM device has a stacked gate structure consisting of a floating gate for storing carriers and a control gate that is separated from the floating gate by a dielectric layer. For example, U.S. Pat. No. 5,479,368 discloses a flash memory cell structure that has two spacer floating gates under a control gate, and U.S. Pat. No. 5,051,793 discloses another flash memory cell structure that has a spacer floating gate surrounding a control gate.
Recently, however, a new category of E2PROM/Flash EPROM devices utilizing charge-trapping mechanism are provided to avoid the leakage problem of the conventional E2PROM/Flash EPROM devices. A trapping-type E2PROM/Flash EPROM usually includes a composite ONO charge-trapping layer disposed between a substrate and a silicon gate, and is therefore called a “SONOS memory”. For example, U.S. Pat. No. 5,966,603 discloses a SONOS memory that stores two bits per cell (2 bits/cell). The SONOS memory is programmed with channel hot electrons and erased with hot holes, wherein hot electrons or hot holes are injected into two coding regions in the charge-trapping layer near the source/drain of a memory cell. In addition, U.S. Pat. Nos. 5,789,776 and 5,774,400 both disclose a SONOS memory cell structure that has a polysilicon gate connected to an upper metal line.
To operate a SONOS memory, however, relatively high voltages from 15V to 18V are required for injecting carriers into or ejecting carriers from the nitride trapping layer since the energy barrier of the bottom oxide layer is quite high (≈9 eV for electrons). Therefore, the power consumption of the conventional SONOS memory device is high, and the circuit design is difficult. For example, some devices in the periphery circuit have to be specially designed to fit with the high voltages, and more voltage-boosting circuit units may be required to achieve the high voltages starting from a relatively low input voltage. In view of this, lowering the required operating voltages is an important issue in the design of trapping-type E2PROM/Flash EPROM devices.